Generally, a manufacturing process of a high voltage semiconductor device requiring high voltage is applied to various technologies such as liquid crystal displays (LCDs), driving integrated circuits, organic light emitting diodes (OLEDs), power integrated circuits, etc.
The manufacturing process of the high voltage semiconductor device can use a method of integrating a high voltage device, a middle voltage device, and a low voltage device in the form of a system on chip (SOC).
The high voltage device manufactured through the manufacturing process of the high voltage semiconductor device should have high voltage operating characteristics, that is, high breakdown voltage characteristic. Therefore, a high-temperature diffusion process is performed for a long time to form a well of a high voltage device. Also, in order to form the well, a photo alignment key is required. Also, in order to form the photo alignment key, a zero process is performed.
The zero process is a process of purely forming the photo alignment key without having a direct relation in implementing an actual device.
In detail, a conventional process for manufacturing a high voltage semiconductor device in the related art will be described with reference to FIGS. 1A to 1D.
FIGS. 1A to 1D are cross-sectional views of a process for explaining a manufacturing method of a semiconductor device for a SOC integrated circuit according to the related art.
First, as shown in FIG. 1A, an oxide film 11 is formed on a semiconductor substrate 10 defined by a key area (Key) to be formed with an alignment key, a low voltage area (LV) to be formed with a low voltage device (or, a middle voltage device), and a high voltage area (HV) to be formed with a high voltage device.
Next, a first mask process is performed to form a first photoresist pattern 12 so that a portion of the semiconductor substrate 10 of the key area is exposed on the oxide film 11.
Next, a trench 14 is formed in the semiconductor substrate 10 of the exposed key area by performing an etching process 13 using the first photoresist pattern 12 as a mask. At this time, the trench 14 serves as the alignment key between the semiconductor substrate 10 and the mask equipment.
Next, as shown in FIG. 1B, after removing the first photoresist pattern 12, a second photoresist pattern 15 is formed on the oxide film 11 including the trench 14 through a second mask process. At this time, the second photoresist pattern 15 is formed to have a structure that a high voltage PMOS area (HPM) to be formed with a high voltage PMOS transistor is opened, on the basis of the alignment key.
Next, the semiconductor substrate 10 of the high voltage PMOS area (HPM) is doped with an N type impurity by performing an ion implant process 16 using the second photoresist pattern 15 as the mask.
Next, as shown in FIG. 1C, after removing the second photoresist pattern 15, a third photoresist pattern 17 is formed on the oxide film 11 including the trench 14 through a third mask process. At this time, a third photoresist pattern 17 is formed to have a structure that a high voltage NMOS area (HNM) to be formed with a high voltage NMOS transistor is opened, on the basis of the alignment key.
Next, an ion implant process 18 is performed using the third photoresist pattern 17 as the mask. Therefore, the semiconductor substrate 10 of the high voltage NMOS area (HNM) is doped with a P type impurity.
Next, as shown in FIG. 1D, after removing the third photoresist pattern 17, the doped N type impurity and P type impurity are diffused by performing a high-temperature thermal diffusion process for a long time. Thereby, the semiconductor substrate 10 of the high voltage PMOS area (HPM) and the semiconductor substrate 10 of the high voltage NMOS area (HNM) are formed with an N-well 19a and a P-well 19b. At this time, a thermal oxide film 20 can be formed on the surface of the semiconductor substrate 10 including the trench 14 by means of the heat applied when performing the thermal diffusion process.
Next, a plurality of device isolating layers for isolating the key area (Key), the high voltage area (HV), and the low voltage area (LV) are formed by performing the shallow trench isolation (STI) process.
Next, the high voltage NMOS and PMOS transistors are formed on the semiconductor substrate 10 of the high voltage area (HV). The low voltage NMOS and PMOS transistors are formed on the semiconductor substrate 10 of the low voltage area (LV), according to the known art.
In other words, as can be appreciated from FIGS. 1A to 1D, the related art forms the photo alignment key required for forming the well in the high voltage device. And, the zero process is performed for forming the photo alignment key.
Therefore, the manufacturing process of the semiconductor device is complicated and the manufacturing cost thereof is higher than desired.